1. Field of the Invention
The present invention relates, in general, to a semiconductor device and, more particularly, to a differential amplifier. This claims priority under 35 USC xc2xa7119(e) (1) of Provisional Application No. 60/348,376, filed on Jan. 16, 2002.
2. Description of the Related Art
FIG. 9 is a block diagram showing a conventional differential amplifier. Referring to FIG. 9, the conventional differential amplifier comprises N-type MOSFET (NMOS transistor) 900-903 and a constant current source 904. Each NMOS transistor has a gate electrode, a source electrode and a drain electrode A supply voltage VDD is applied to the gate and drain electrodes of NMOS transistor 902. Also, the supply voltage VDD is applied to the gate and drain electrodes of NMOS transistor 903. FIG. 10 shows voltage-current characteristic of the NMOS transistors 902 and 903. The curved line shows the drain current of each NMOS transistors 902 and 903 relative to the gate-to-source voltage VGS. In a region A of the diagram, the NMOS transistors 902 and 903 are considered to be in an off-state, and in a region B of the diagram, the NMOS transistors 902 and 903 are considered to be in an on-state.
The operation of the conventional differential amplifier will be described with reference to FIGS. 9-11. FIG. 11 is a timing chart for explaining of the operation of the conventional differential amplifier when input with pulse signals, for example, clock signals. When a pulse signal IN1 having a rising edge is input to the gate electrode of the NMOS transistor 900, the NMOS transistor 900 rapidly changes its state from an off-state to an on-state. In this case, the voltage VGSb which is larger than the threshold voltage Vt is applied to between the gate and the source electrodes of NMOS transistor 902. The NMOS transistor 902 is considered to be in the region B. A parasitic capacitance which is provided between the drain and the source electrodes of the NMOS transistor 902 is charged. Therefore, the voltage level of an output signal OUT1 changes from a high voltage level to a low voltage level almost immediately.
On the other hand, when the pulse signal having a falling edge is input to the NMOS transistor 900, the NMOS transistor 900 changes its state from an on-state to an off-state, thus causing the source electrode of the NMOS transistor 902 to quickly become an open state. The parasitic capacitance of the NMOS transistor 902 is discharged, thus causing the voltage level of the output signal OUT1 to rise. A speed changing the voltage level from a low level to a high level depends on a discharge speed of the parasitic capacitance. Therefore, it takes a relative long period of time xcex94T to change the voltage level of the output signal OUT1 from low voltage level to high voltage level. As seen in FIG. 11, the voltage level of the output signal OUT1 rises slowly. The same is true for the output signal OUT2.
Therefore, in the conventional difference amplifier, it takes a relatively long period of time xcex94T to change the voltage level of the output signal from a low voltage level to a high voltage level, and distortions of the output signal thus become large.
According to one aspect of the present invention, there is provided a differential amplifier includes a first diode which has a first terminal and a second terminal wherein the first terminal of the first diode is coupled to a voltage node and wherein the second terminal of the first diode is coupled to a first node, a second diode which has a first terminal and a second terminal wherein the first terminal of the second diode is coupled to the voltage node and wherein the second terminal of the second diode is coupled to a second node, a first transistor which is coupled to the first node in series with the first diode and which has a control terminal coupled to a first input terminal, a second transistor which is coupled to the second node in series with the second diode and which has a control terminal coupled to a second input terminal, and a bias current supply which is coupled to the first and second nodes to bias the first and second diodes.